Modern system-on-chip (SOC) devices often utilize multiple clocks that produce different clock domains within the same chip. Issues associated with clock domain crossings include metastability, data loss, and data incoherency. Metastability is caused when signals transition close to active clock edges such that setup or hold violations cause an output signal to oscillate indefinitely until a later clock signal settles it to a stable value. Systems often utilize synchronizer logic circuits used to transmit data between different clock domains to avoid metastability and other problematic timing conditions. Synchronizers generally comprise flip-flop circuits that introduce signal delays to allow oscillations to settle down to produce a stable output at the destination domain.
Predictive synchronizers have been developed that use information about the transmitting and receiving clock domains to decrease both failure rate and data transmission latency. Predictive synchronization is advantageous in that it is low latency (assuming the prediction data is correct) and can completely avoid the chance of metastability. However, if the clock frequency in either the receive or transmit domains goes outside of an acceptable range due to drift or active ramping then miss-predictions may occur. Such miss-predictions cause a high chance of metastability which breaks any logic connected to the synchronizer and defeats the purpose of the synchronizer. Existing predictive synchronizers have generally used high latency measurement circuits to get the information they need from the transmit and receive clock domains, and these systems expect transmit and receive frequencies to stay within a certain range around the measured value during the entire operation. Existing predictive synchronizers thus require information collected from frequency measurement circuits with high latency. This information is acquired during a measurement state and is not revisited during normal operation, with the system assuming that frequencies will stay within a small range. This means that if either clock frequency (receive/transmit or source/destination) goes outside of the acceptable range due to frequency drift or active ramping then miss-predictions will occur causing a high chance of metastability.
Although current predictive synchronizer designs perform satisfactorily when used with static frequency devices, many SOC devices purposely utilize frequency drift or frequency ramping within one or more domains to enhance certain performance or operating characteristics. For example, active frequency ramping (up or down) occurs in a number of SOCs and is a key mechanism in devices that feature dynamic frequency scaling (DFS) or dynamic voltage scaling (DVS) whereby performance or power consumption of the device is reduced based on work load or operational characteristics to save power or reduce the amount of heat generated by the device. Present predictive synchronizer circuits are of limited usefulness in such SOC devices because of their inability to efficiently accommodate dynamic frequency changes in different clock domains.
A particular predictive synchronizer has been developed for periodic clock domains in which two versions of data are latched and selected according to the output of a phase comparator that compares the two domain clocks. As stated above, such a circuit requires advanced knowledge of the transmit and receive frequencies and is non-adaptive with respect to changing or ramping frequencies. Certain other predictive synchronizers have been developed that accommodate variable frequencies, however such systems generally do not provide continuous frequency measurement and uninterrupted synchronization. In general, present predictive synchronizers use measurement circuits to get the information they need from the transmit and receive clock domains. These circuits require many cycles to complete measurement and must be restarted for every change in receive or transmit clock frequency. Thus, existing predictive synchronizers require information collected from measurement circuits with high latency.
What is needed, therefore, is a system and method provides frequency information directly to a predictive synchronizer as soon as the frequency changes in either or both of the transmit and receive clock domains in order to eliminate the latency associated with the frequency measurement circuits used in present heterochronous synchronizer systems.
The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches.